The parallel port can be accessed either directly (specify the
io_addr variable, below) or through the kernel driver (specify
The bits are arranged into three registers, D, S and C. Register D can be either input or output, S is always input. The C register is usually output, but it can be used as input if the port is accessed directly (not through the kernel driver) and the hardware supports it, which varies between manufacturers. The direction of these configurable registers is inferred from the mapping; or you can specify it directly.
The format of the
<io_addr> column for the map is
R.x where R is the register (D, S or C) and x is the bit
number. The acceptable address ranges are listed in the table.
|C||C.0-C.3||4||usually output||TTL Open Collector||1/14/16/17|
Note that while some of the S and C bits are inverted by the parallel port hardware, this module re-inverts all these bits to present a coherent positive logic interface. However, you may wish to verify the boot-up status of those used as outputs to avoid unexpected actions during startup.
io_addr = 0x378
NOTE: this is unrelated to the
<io_addr> column of
dev_file = /dev/plc_parport0
NOTE: If both of the above methods of accessing the parallel port are configured, then the kernel driver will be used. Only if this method fails will it fall back to the direct access mode, using the specified (or default) io base address.
Ddir = out
Cdir = in
See warnings above about using the C register for input.
The S register is always input; its direction is not configurable.
# use this device dev_file = /dev/plc_parport0 # fallback to this hardware address io_addr = 0x278 # Use these four bits as outputs; they're wired to light up when the output # is low, so we invert them here. # This also automatically configures the D register for output. map inv out D.0 L1 map inv out D.1 L2 map inv out D.2 L3 map inv out D.3 L4
$Date: 2004/12/28 05:32:11 $