Parallel port I/O

Introduction

The parallel port has 17 usable bits of I/O, some of which can be configured either as input or as output. Up to 12 can be configured as outputs, and depending on the hardware and access method either 13 or all 17 can be configured as inputs.

The parallel port can be accessed either directly (specify the io_addr variable, below) or through the kernel driver (specify dev_file).

The bits are arranged into three registers, D, S and C. Register D can be either input or output, S is always input. The C register is usually output, but it can be used as input if the port is accessed directly (not through the kernel driver) and the hardware supports it, which varies between manufacturers. The direction of these configurable registers is inferred from the mapping; or you can specify it directly.

The format of the <io_addr> column for the map is R.x where R is the register (D, S or C) and x is the bit number. The acceptable address ranges are listed in the table.

Register	Range	Number	Direction	Note	Pins
D	D.0-D.7	8	output/input	LS TTL	2-9
S	S.3-S.7	5	input	LS TTL	15/13/12/10/11
C	C.0-C.3	4	usually output	TTL Open Collector	1/14/16/17

Note that while some of the S and C bits are inverted by the parallel port hardware, this module re-inverts all these bits to present a coherent positive logic interface. However, you may wish to verify the boot-up status of those used as outputs to avoid unexpected actions during startup.

Configuration

io_addr

The parallel ports base address. 0x378 is the default if no io_addr is specified. You may also like to try 0x278 if the first doesn't work.

Example: io_addr = 0x378

NOTE: this is unrelated to the <io_addr> column of the map.

dev_file

If you prefer to go though the kernel driver, then specify the device file.

Example: dev_file = /dev/plc_parport0

NOTE: If both of the above methods of accessing the parallel port are configured, then the kernel driver will be used. Only if this method fails will it fall back to the direct access mode, using the specified (or default) io base address.

Ddir

defines the direction {in | out} the D register should use. If this is omitted, it will be automatically inferred from the mapping.

Example: Ddir = out

Cdir

defines the direction {in | out} the C register should use. If this is omitted, it will be automatically inferred from the mapping.

Example: Cdir = in

See warnings above about using the C register for input.

The S register is always input; its direction is not configurable.

Example

# use this device
dev_file = /dev/plc_parport0
# fallback to this hardware address
io_addr = 0x278

# Use these four bits as outputs; they're wired to light up when the output
# is low, so we invert them here.
# This also automatically configures the D register for output.
map inv out D.0 L1
map inv out D.1 L2
map inv out D.2 L3
map inv out D.3 L4

$Date: 2004/12/28 05:32:11 $